Complementary metal-oxide-semiconductor (CMOS) technology is the dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Conventional CMOS technology employs (100) silicon wafer as the starting material for volume production. Such silicon wafers have a surface that is (100) oriented, i.e., the normal to the silicon wafer surface is in the [100] direction. Hence, conventional planar metal-oxide-semiconductor field-effect transistors (MOSFETs) formed on (100) silicon wafers have a gate dielectric-channel interface plane that is in the (100) plane of the silicon substrate.
Commercial CMOS technology universally uses (100) oriented silicon wafers because of their low surface state density on the order of 1010 per square centimeter on thermally oxidized surfaces. This compares with surface state densities in the order of 1011 per square centimeter on thermally oxidized surfaces with other crystal orientations such as the (110) and (111) planes. Another advantage is the high surface mobility of electrons on the (100) plane, as disclosed in “Mobility anisotropy of electrons in inversion layers in oxidized silicon surfaces,” Physical Review B, vol. 4, no. 6, (15 Sep. 1971), pp. 1953.
As a result, an n-channel transistor formed on a silicon substrate with (100) surface provides the largest source-to-drain current. Another benefit of using (100) wafers is the ease of cleavage or cutting along (110) planes. This property is useful when dicing up processed wafers into separate dies prior to packaging, since the equivalent (110) planes intersect with the (100) silicon surface to form squarish shapes. However, the measured mobility of holes in a p-channel transistor is nearly the smallest when the gate dielectric-channel interface is in the (100) plane as compared to other crystal planes.
Size reduction of the transistor has provided significant improvement in the speed performance, circuit density, and cost per unit function of semiconductor chips over the past few decades. Significant challenges are faced when transistors are scaled into the sub-100 nm regime. This has resulted in research efforts on further improvement of n-channel and p-channel transistor performance using alternative techniques besides transistor scaling, such as the use of strain-induced band-structure modification and mobility enhancement to increase the transistor drive current. Another potential way to improve transistor performance is to explore the use of silicon substrates with non-conventional crystal orientations as the starting wafer.
U.S. Pat. No. 4,857,986, entitled “Short channel CMOS on (110) crystal plane” issued to M. Kinugawa, discloses the formation of CMOS transistors on a monocrystalline silicon substrate having a (110) crystal orientation. In U.S. Pat. No. 6,335,231, entitled “Method of fabricating a high reliable SOI substrate” issued to S. Yamazaki et al., a silicon-on-insulator substrate is fabricated having a main crystal surface that is (110) oriented. Both of these references use a (110) oriented silicon surface for both, the n-channel and p-channel planar transistors fabricated on these substrates have a gate dielectric-channel interface that is in the (110) plane.
In U.S. Pat. No. 4,768,076 ('076), entitled “Recrystallized CMOS with different crystal planes” issued to M. Aoki et al., a CMOS integrated chip is formed on a semiconductor crystalline surface having a plane azimuth (110) or (023) in order to increase the speed of operation. The semiconductor devices described in the '076 patent are stacked.
In U.S. Pat. No. 6,483,171 entitled “Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming the same” issued to L. Forbes et al., a method for forming n-channel and p-channel transistors that includes cutting a substrate along a higher order orientation and fabricating vertical deep sub-micron n-channel and p-channel transistors on the substrates is provided. In this patent, the vertical transistors have a source-to-drain direction that is perpendicular to the surface of the wafer.
In U.S. Pat. No. 5,384,473, entitled “Semiconductor body having element formation surfaces with different orientations,” issued to S. Yoshikawa et al., a semiconductor body is constructed such that a portion of a semiconductor substrate has a first surface plane and another portion of a second semiconductor substrate has a second surface plane.
In U.S. Pat. No. 4,933,298, entitled “Method of making high speed semiconductor device having a silicon-on-insulator structure” issued to M. Hasegawa, a CMOS silicon-on-insulator structure is fabricated by using a silicon substrate with (110) orientation and a silicon layer with (100) orientation. Openings are formed in the insulator to expose the (110) oriented substrate. Silicon regions are then formed with (110) orientation using the (110) substrate as a template. This method uses solid phase epitaxial growth rate.